MOS static type RAM having a variable load

ABSTRACT

An MOS static type RAM has a memory cell array comprising of a plurality of static type memory cells arranged in matrix, a plurality of data lines connected to the data input-output terminals of the respective memory cells and a plurality of word lines connected to the selection terminals of the respective memory cells. Data line load circuits are disposed between the power terminal of the circuit and the data lines. Each data line load circuit is kept at a relatively high impedance in the data write-in operation, and at a relatively low impedance in the data read-out operation. The use of the data line load circuits comprised of such variable impedance circuits can speed up the operating speed of the RAM and can accomplish lower power consumption.

This is a continuation of application Ser. No. 740,550, filed June 3, 1985 now U.S. Pat. No. 4,760,561 issued 7-26-88.

BACKGROUND OF THE INVENTION

This invention relates to a static type RAM (random access memory) comprising MOSFETs (insulated gate field effect transistors), and to a technique which is effective when applied to a RAM constituted by a CMOS (complementary MOS) circuit, for example.

A memory cell in an MOS static type RAM is comprised, for example, of a static type flip-flop circuit comprising a pair of driving MOSFETs whose gates and drains are mutually cross-coupled and its load element, and a pair of transfer gate MOSFETs. A memory array includes a plurality of such memory cells arranged in a matrix and a plurality of complementary data line pairs to which input-output terminals of the corresponding memory cells are respectively connected. A load element comprising, for example, an MOSFET which is continuously turned on, is interposed between each complementary data line and the power terminal of the circuit. (For a RAM having a structure in which the load resistors are connected to the data lines, refer to U.S. Patent Specification No. 4,272,834, for example.)

The load resistors connected to the complementary data lines operate in such a fashion as to set the potential of the complementary data lines to a predetermined potential before a data read-out operation from the memory cells and before a data write-in operation into them. The access time of the memory in the data read-out and write-in operations can be made constant by the previous setting of the potential of the complementary data lines.

As a result of studies, however, the inventors of the present invention have found that the following problems occur when fixed resistance loads constituted by MOSFETs described above are used.

In the data read-out operation, a predetermined word line is selected, thereby selecting a certain memory cell. Then, the level of a pair of complementary data lines is determined by the selected memory cell. In this case, the read-out low level of one of the complementary data lines is determined by the conductance ratio of the conductance characteristics of the driving MOSFETs and transfer gate MOSFETs to the conductance characteristics of the load MOSFETs. When a plurality of memory cells are sequentially selected in order to continuously read out the data (stored information) stored in a plurality of memory cells, the levels of the complementary data lines are sequentially determined by the selected memory cells. In this case, if data of the opposite level is read out such as when the stored information of a logic "1" is read out after the read-out of the stored information of a logic "0", for example, the levels of the complementary data lines are changed by a large amount from the high and low levels to the low and high levels, respectively. Here, the level changing speed of each complementary data line is limited by unnegligible capacitance which comprises a parasitic capacitance and a stray capacitance coupled to the complementary data lines. As a result, the data read-out speed is restricted.

The inventors of the present invention pay specific attention to the fact that when the level change width of each of the complementary data lines is reduced, the time of the change from one level to the other can be reduced, that the charge-up speed to the complementary data lines can be increased by increasing the conductance of the load MOSFETs and the level change width of the complementary data lines can be reduced, as well. Therefore, the inventors have examined the possibility of increasing as much as possible the conductance of the load MOSFETs in order to realize a high speed read-out operation.

It has been found, however, that the following new problem develops. That is, the read-out operation is substantially effected for a memory cell which is coupled to the unselected complementary data lines in the write-in operation and which is selected by the word line. Therefore, if the conductance of the load MOSFETs are increased, a relatively great current flows between the load MOSFETs and the selected memory cells. A current flowing between the memory cell coupled to the unselected complementary data line and the load MOSFET is irrelevant to the write-in data; hence, it is essentially a wasteful current. However, the read-out speed will be reduced if the conductance characteristics of the load MOSFETs are reduced in order to reduce this wasteful current.

SUMMARY OF THE INVENTION

An object of the present invention is to provide an MOS static type RAM which operates at high speed and consumes little power.

Other objects and novel features of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

Among the inventions disclosed herein, the following is a typical example.

Load means disposed in a pair of complementary data lines of a memory cell array is comprised of a variable load means which are controlled by a control signal in such a fashion that the impedance thereof is increased to greater level in a data write-in operation than in a data read-out operation or when the chip is not being accessed. This arrangement accomplishes the high speed operation and the lower power consumption described above.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram showing one embodiment of the present invention;

FIG. 2 is a circuit diagram showing another example of its load circuit;

FIG. 3 is a diagram useful for explaining the voltage characteristics of its read-out level; and

FIG. 4 is a circuit diagram showing still another example of the load circuit.

DESCRIPTION OF THE PREFERRED EMBODIMENTS [Embodiment 1]

FIG. 1 is a circuit diagram of one embodiment of the present invention. Though not particularly limited to this configuration, a RAM shown in the diagram is formed on one semiconductor substrate such as single crystal silicon by the well-known CMOS (complementary metal-insulator-semiconductor) integrated circuit (IC) technique.

MOSFETs constituting memory cells are of the N-channel type and are formed on P-type well regions that are in turn formed on an N-type semiconductor substrate. P-channel MOSFETs are formed on the N-type semiconductor substrate. The P-type well region which acts as a substrate gate for the N-channel MOSFETs is connected to a ground terminal of a circuit, and the N-type semiconductor substrate which acts as a common substrate gate for the P-channel MOSFETs is connected to a power terminal of the circuit. The structure in which the MOSFETs constitute the memory cells in the well regions is effective for preventing the erroneous inversion of data stored in the memory cells, said inversion being induced by α-particles and the like.

Terminals A_(x), A_(y), D_(in), D_(out), WE, CS, V_(cc) and GND are external terminals for the integrated circuit.

A memory array M-ARY is constructed of a plurality of memory cells MC that are arranged in matrix, word lines W_(o) through W_(n) and complementary data lines D_(o), D_(o) through D₁, D₁.

The memory cells MC have the same construction. As represented by one of their specific circuits, each memory cell MC is constructed of memory MOSFETs Q₁ and Q₂ whose gates and drains are cross-connected with each other and whose sources are connected to a ground point GND, and high resistance resistors R₁ and R₂ that are disposed between the drains of these MOSFETs Q₁ and Q₂ and the power terminal V_(cc), respectively, and that are comprised of a polycrystalline silicon layer. Transfer gate MOSFETs Q₃ and Q₄ are interposed between the common junctions of MOSFETs Q₁ and Q₂ and the complementary data lines D₀ and D₀, respectively. The gates of the transfer gate MOSFETs Q₃, Q₄ and the like that are disposed in the same row are connected in common to the corresponding word lines W₀, W₁ and W_(n) as typically shown in the circuit diagram. The input/output terminals of the memory cells disposed in the same column are connected to the corresponding pair of complementary data (or bit) lines D₀ and , D₀, D₁ and D₁, and the like as also typically shown in the drawing.

The gate electrodes of the transfer gate MOSFETs Q₃ and Q₄ are regarded as the selection terminals of the memory cells, and the current transfer electrodes or source-drain electrodes connected to the data lines D₀, D₀ of the transfer gate MOSFETs Q₃ and Q₄ are regarded as the data input/output terminals of the memory cell.

In the memory cell, though the MOSFETs Q₁, Q₂ and the resistors R₁,R₂ constitute a kind of flip-flop circuit, the operating point in the data retention state is different from that of flip-flop circuits in the ordinary meaning of the term. That is, the resistor R₁ of the memory cell MC described above has an extremely high resistance value so that the gate voltage of MOSFET Q₂ when MOSFET Q₁ is turned off is a little bit higher than the threshold voltage of Q₂, in order to accomplish low power consumption. Similarly, R₂, too, has an extremely high resistance value. This means that both the resistors R₁ and R₂ have high resistance so that they can compensate for the drain leakage current of MOSFETs Q₁ and Q₂. The resistors R₁ and R₂ have a current supply capacity such that they prevent the discharge of the data charge stored in the gate capacitance (not shown) of MOSFET Q₂. For example, the drain leakage current of MOSFETs Q₁ and Q₂ is typically on the order of 10⁻¹² amperes. The resistors R₁ and R₂ are on the order of about 10 giga-ohms so as to correspond to the drain leakage current.

In accordance with this embodiment, although the RAM is produced by the CMOS-IC technique, the memory cell MC is constituted from the N-channel MOSFETs and the polysilicon resistance elements as described above.

The sizes of the memory cells and memory array of this embodiment can be reduced when compared with the case where P-channel MOSFETs are used in place of polysilicon resistance elements. In other words, when a polysilicon resistor is used, it can be formed integrally with the gate electrode of the driving MOSFET Q₁ or Q₂, and its own size can be made compact. If a P-channel MOSFET is used, on the other hand, it must be spaced relatively far from the driving MOSFETs Q₁ and Q₂. The use of a polysilicon resistor eliminates such unnecessary space on the semiconductor substrate.

In the drawing, the word line WO is selected by the output signal which is generated by a NOR gate circuit G₁ constituting an X address decoder X-DCR. This also applies to other word lines W₁, . . . , W_(n).

The X address decoder X-DCR described above is constructed of NOR gates G₁, G₂, G₃ and the like that are similar to one another. Internal complementary address signals generated by an X address buffer X-ADB receiving an external address signal AX consisting of a plurality of bits (that is, an address signal produced from a suitable circuit device, not shown) are applied in a predetermined combination to the input terminals of these NOR gates G1, G2, G3. In order to prevent unnecessary power consumption at the time of the read-out operation through the memory cells, a timing signal φ is applied in common to these NOR gates G₁ -G₃, though the arrangement is not limited to this configuration. The data stored in the selected memory cell is supplied to the complementary data lines by the high level (logic "1") of the timing signal φ, and thereafter the word line that has been selected by the read-out operation of the stored data is put into the non-selected state.

The pairs of the complementary data lines D₀, and D₀ and D₁, D₁ in the memory cell described above are connected to common complementary data lines CD, CD through a column switch circuit C-SW consisting of the transfer gate MOSFETs Q₁₃, Q₁₄ and Q₁₅, Q₁₆ for the selection of data lines, respectively. A pair of input terminals of a read-out circuit RA and a pair of output terminals of a write-in circuit WA are connected to the common complementary data lines CD, CD. The read-out circuit RA delivers a read-out signal to a data output terminal D_(out), while the write-in circuit WA receives a write-in data signal supplied from a data input terminal D_(in). In the active state, the write-in circuit WA sends a complementary level write-in data signal to the complementary data lines CD,CD.

The read-out circuit RA is controlled in its operation by a control signal φr supplied from a control circuit CONT. The read-out circuit RA differentially amplifies data signals of the common complementary data lines CD and CD, and sends the amplified data signal output terminal D_(out) when the read-out circuit is rendered to an operative state. When the read-out circuit is in the inoperative state, the output terminal of the read-out circuit RA is in the high impedance state or the floating state.

The write-in circuit WA is controlled in its operation by the control signal φw. When operative, the write-in circuit WA produces a complementary data signal corresponding to the input data, that is supplied to the data input terminal D_(in), to the common complementary data lines CD, CD. When the write-in circuit WA is inoperative, the pair of its output terminals are in a high impedance state or the floating state.

Selection signals Y₀ and Y₁ generated by a Y address decoder Y-DCR are applied to the gates of the MOSFETs Q₁₃, Q₁₄ and Q₁₅, Q₁₆ that constitute the column switch. The Y address decoder Y-DCR is constituted of NOR gates G₄ and G₅ that are similar to each other. The internal complementary address signals generated by a Y address buffer Y-ADB receiving an external address signal AY comprising a plurality of bits (that is, an address signal produced from a suitable circuit not shown) are applied in a predetermined combination to these NOR gates G₄, G₅.

Upon receiving the control signals from external terminals WE, CS, the control circuit CONT produces the internal control timing signal φ and the like described above.

When a chip selecting signal applied to the external terminal CS is at the high level, that is, at a chip non-selecting level, the internal control timing signal φ is held at the high level in response thereto. The internal control timing signal φ falls to the low level when the chip selection signal is changed to the low level and a write enable signal supplied to the external terminal WE is changed to the low level, that is, when a write-in operation mode is designated. The internal timing signal φ is changed to the low level for a predetermined period when the chip selecting signal is at the low level under the high level state of the write enable signal, and when the address signal AX is changed under the chip selection state,

A circuit for producing such a timing signal φ can be constituted by a suitable combination of heretofore known circuits such as address transient detection circuits, gate circuits, delay circuits, and the like.

In this embodiment, the following circuit elements are disposed as load means coupled to the pairs of complementary data lines D₀,D₀ and D₁, D₁.

N-channel MOSFETs Q₅ to Q₈ which act as fixed resistor elements are disposed in the data lines D₀ -D₁, respectively. N-channel MOSFETs Q₉ through Q₁₂ are connected parallel to these transistors Q₅ -Q₈, respectively, in order to speed up the inversion read-out operation. The MOSFETs Q₅ -Q₈ are rendered to a continual operation state when their commonly connected gates and drains are supplied with the power source voltage V_(cc). The conductance of each of these transistors Q₅ -Q₈ is set to be sufficiently smaller than the combined conductance of the data storage MOSFETs Q₁, Q₂ and the transfer gate MOSFETs Q₃, Q₄ so that the difference between the high level and low level of the complementary data lines, that is determined by the memory cell, becomes sufficiently great. For example, the conductance characteristics of these MOSFETs Q₅ through Q₈ are set so that the high level of the complementary data lines D₀, D₀ is 3.5 V and the low level is from 0.5 to 1 V so that the voltage difference ΔV may be as great as 3 V.

The lower limit of conductance or the upper limit of impedance of MOSFETs Q₅ -Q₈ is set to values that can compensate for at least the leakage current which develops at the junction of the transfer gate MOSFETs Q₃ and Q₄ in the memory cell.

The conductance of each MOSFET formed on one semiconductor substrate by the semiconductor integrated circuit technique is determined by the ratio of its channel width W to its channel length L (i.e., W/L). The ratio W/L is 5.8 μm/2 μm (referred hereinafter as 5.8/2) for MOSFETs Q₁ and Q₂ and 2.3/2 for MOSFETs Q₃ and Q₄ of the memory cell, though the invention is not limited to these values. The ratio W/L of MOSFETs Q₅ through Q₈ is 2.3/16, for example, is in accordance with the ratios W/L of MOSFETs Q₁ through Q₄.

Though not particularly limited to this configuration, each channel MOSFET is arranged in the enhancement mode, and has a threshold voltage of +0.8 V.

In accordance with this embodiment, it is possible to prevent abnormal drop of the potential on the complementary data lines during the period such as the data write-in period because MOSFETs Q₅ through Q₈ are provided. In other words, during the data write-in period, the pair of data lines that are not selected by the column switch C-SW have their levels determined by the selected memory cell. If, for example, MOSFETs Q₁₃ and Q₁₄ constituting the column switch C-SW are turned off and the word line W0 is at the selection level, the levels of the unselected data lines D₀ and D₀ are determined by the memory cell which is coupled to the word line W₀. Here, the memory cell itself that has the high resistance elements R₁ and R₂ such as shown in the drawing, does not substantially have a driving capacity that keeps the data lines at the high level. Therefore, unless MOSFETs Q₅ and Q₆ are provided, the data line among the unselected data lines D₀ and D₀ which is to be set to the high level is substantially in the floating state. If the data lines D₀ and D₀ and are kept in the unselected state for a relatively long period during the write-in period in response thereto, therefore, the level of the data line among them which is to be kept at the high level is lowered abnormally by the leakage current. When MOSFETs Q₅ and Q₆ are disposed as shown in the drawing, however, this abnormal drop of the complementary data line potential can be prevented, so that any adverse influences upon the access time to the memory cell can be avoided.

An internal control signal WE CS produced from the control circuit CONT is applied to the gates of MOSFETs Q₉ through Q₁₂. Therefore, these transistors Q₉ -Q₁₂ are turned off only during the write-in operation (that is, when both the chip selection signal CS and the write enable signal WE are at the low level) because the control signal WE CS is at the low level only at that time. The MOSFETs Q₉ -Q₁₂ are kept ON during the read-out operation and under the chip non-selection state. MOSFETs Q₉ -Q₁₂ under the ON state constitute load elements to the corresponding complementary data lines in cooperation with MOSFETs Q₅ -Q₈. The conductance of the load element in this case is set to a value such that the level difference to be set by the selected memory cell between a pair of complementary data lines is as small as possible. For example, the value is selected so that one of the complementary data lines is at the high level of 3.5 V and the other, at the low level of 3 V so that the voltage difference ΔV may be as small as 0.5 V, at the power source voltage V_(cc) of 5 V. The conductance characteristics of MOSFETs, such as those of Q₉, for example, are set in response to the former in consideration of the relation between the combined conductance characteristics with MOSFET Q₅ connected in parallel with Q₉ and the combined conductance characteristics of the transfer gate MOSFETs in the selected memory cell MC and the driving MOSFETs in the ON state, and also in consideration of the level difference that is to be obtained between the complementary data lines. If MOSFETs Q₁ -Q₄ and Q₅ -Q₈ have the W/L ratios such as described above, the W/L ratio of MOSFETs Q₉ through Q₁₂ is set to 16/2, though the arrangement is not limited to this value.

The level difference given to the complementary data lines during the data read-out operation is applied to the read-out circuit RA through one set of column switch MOSFETs Q₁₃ -Q₁₆ and through the common complementary data lines CD, CD. The read-out circuit RA has a differential amplification function. Therefore, the level difference between the complementary data lines necessary for the data read-out operation may be relatively small, as described above.

In this embodiment, the timing φ described above is used in order to bring all the word lines into the unselected state after the stored data of the memory cell MC is supplied to the complementary data lines and when the chip is not being selected. The timing signal φ is at the low level (logic "0") during the period from the start of the selection of the word lines in the read-out operation to the occurrence of the predetermined level difference between the corresponding complementary data lines, and during the write-in operation, and is at the high level at other periods. The reason why the word lines are brought into the unselected state by the timing signal φ after the completion of the read-out operation of the stored data from the memory cell MC and during the time when the chip is not being accessed is as follows. Unless a control signal such as the timing signal φ is used, one of a plurality of word lines is brought to the selection level by the operation of the X address decoder X-DCR when the chip is not being selected. The memory cell coupled to the word line at the selection level forms a current path between one of the pair of complementary data lines and the grounding point of the circuit. In this case, therefore, a direct current continues to flow through the load circuit comprising MOSFETs Q₅, Q₉ and the like that are turned ON, the transfer gate MOSFETs of the selected memory cell MC, and the data storage MOSFETs that are turned ON, and wasteful current increases.

When all the word lines are brought into the non-selection level by the timing signal φ as in this embodiment, all the memory cells are also brought into the unselected state in response thereto, so that the increase of the wasteful current such as described above can be prevented.

In this embodiment, since the read-out level of the complementary data lines is reduced to a minimum necessary level during read-out by reducing relatively the impedance of the load circuit of the data lines (or by increasing the conductance characteristics), the inversion read-out can be done at high speed. The level of the complementary data lines in the previous operation can be reset at a high speed by reducing relatively the impedance of the load circuit during the chip selection period, and hence the next read-out operation can be made rapidly. At this time, since the timing signal φ prevents the occurrence of the wasteful current, low power consumption can be accomplished.

In the write-in operation, on the other hand, the high and low levels are applied from the write-in circuit WA to the selected complementary data lines, but the low level of the data lines can be reduced to a lower potential by increasing the impedance of the load circuit. This makes it possible to execute the write-in operation at a higher speed. Since the impedance of the load circuit is increased in this case, the wasteful current flowing through all of the remaining memory cells MC coupled to the unselected complementary data lines can be reduced. Therefore, lower power consumption can also be accomplished.

The write-in operation can be made at an arbitrary timing by the write enable signal WE. Therefore, when the write-in operation is necessary, it is not suitable to employ the method which brings the word lines into the unselected state after the passage of a predetermined period from the start of selection to the completion of the read-out operation of the stored data of the memory cell MC, as in the read-out operation, thereby reducing required power.

The control signal WE·CS applied to the gates of MOSFETs Q₉ through Q₁₂ is changeable. These MOSFETs Q₉ -Q₁₂ may also be controlled, for example, by a control signal WE·CS which represents the combination of the chip selection signal CS with the write enable signal WE. When this control signal WE·CS is used, MOSFETs Q₉ -Q₁₂ are turned ON in the chip detecting state (that is CS: low level), and the read-out operation mode (that is, WE: high level). Even when the control signal is thus changed, it is possible to obtain the signal level difference necessary for the data lines at the time of read-out and write-in operations. The power consumption does not substantially change. However, when the control method of MOSFETs Q₉ -Q₁₂ is changed in this manner, it is to be noted that the access time of the memory unavoidably becomes relatively longer.

For example, when the chip selection signal CS is brought to the non-selecting level after the execution of the data write-in operation, MOSFETs Q₉ -Q₁₂ are kept OFF in the same way as in the data write-in operation. In this case, the data line that has been set in advance to the low level by the memory cell among a plurality of data lines starts changing to the initial level of the high level due to MOSFETs Q₅ -Q₈. However, the changing speed of the low level data line is greatly limited by the parasitic capacitance of each data line and by the small conductance of MOSFETs Q₅ -Q₈. As a result, each data line is not always at a satisfactory initial level when the chip is first accessed for a data read-out operation. A satisfactory initial level is ensured for the first time by the ON operation of MOSFETs Q₉ through Q₁₂ when the chip is first accessed for a data read-out operation.

When the control signal WE·CS is used as in this embodiment, MOSFETs Q₉ -Q₁₂ are turned ON when chip accessing stops. Therefore, each data lines is set to the satisfactory initial level when the chip is not being accessed; hence, rapid read-out becomes possible.

[Embodiment 2]

FIG. 2 is a circuit diagram showing another example of the data line load circuit in the memory array. Circuits not shown in FIG. 2 are substantially the same as those shown in FIG. 1.

In this embodiment, a series circuit comprising of a P-channel MOSFET Q₁₈ (Q₂₀) and an N-channel MOSFET Q₁₇ (Q₁₉) is connected in parallel with the load circuit shown in FIG. 1 in order to improve the power source dependency characteristics of the read-out level (ΔV). The power source voltage V_(cc) is constantly applied to the gate and drain of the N-channel MOSFET Q₁₇ (Q₁₉) in the same way as in the embodiment shown in FIG. 1. Since the internal control signal WE·CS is applied to the gate of the P-channel MOSFET Q₁₈ (Q₂₀), this transistor is turned ON during the read-out operation and the chip unselected period and is turned OFF during the write-in operation in the same way as the N-channel MOSFET Q₉ (Q₁₀).

Next, the purpose and the construction of such a series circuit of MOSFETs Q₁₈ (Q₂₀) and Q₁₇ (Q₁₉) will be explained.

The combined conductance (impedance) of the N-channel MOSFETs Q₅ and Q₉ (Q₆, Q₁₀) that are turned on by the power source voltage V_(cc) and the control signal WE·CS formed by the power source voltage V_(cc) is relatively great; hence, the combined conductance can be regarded as keeping substantially a constant value irrespective of the drop of the power source voltage V_(cc). In contrast, the driving MOSFET Q₁ (Q₂) and the transfer gate MOSFET Q₃ (Q₄) of the memory cell MC are dropped with respect to gate voltage in response to the drop of the power source voltage V_(cc), so that their conductance reduces by a relatively large amount. For this reason, the level of the data line to be set to the low level between the complementary data lines D₀ and D₀ rises toward the high level as represented by a broken line in the power source voltage characteristic diagram of FIG. 3 because the ratio of conductance of the load circuit to that of the memory cell changes when the power source voltage V_(cc) drops. As a result, the level difference (ΔV) imported to the complementary data lines D₀ and D₀ by the memory cell, becomes small, and the margin of the read-out level deteriorates.

The decrease of the voltage difference between the data lines due to such an undesirable change of the conductance ratio can be substantially prevented by MOSFETs Q₁₇ and Q₁₈.

The P-channel MOSFET Q₁₈ constitutes a variable impedance element which is responsive to the change of the power source voltage V_(cc). This transistor Q₁₈ is turned ON when the control level WE·CS is brought to the low level during the read-out operation. The impedance at this time is increased because the gate-source bias voltage is reduced to a small level in response to the drop of the power source voltage V_(cc).

The N-channel MOSFET Q₁₇ substantially constitutes a level shift element. The high level given to the data line D₀ is substantially limited to a value V_(cc) -V_(th) limited by the threshold voltage V_(th) of MOSFET Q₁₇. The restriction of the high level of the data line D₀ provides the following advantage.

The gate-source voltage of the N-channel MOSFET Q₁₃ constitutes the column switch C-SW shown in FIG. 1 is reduced if the signal to be transferred is at the high level. Therefore, MOSFET Q₁₃ comes to possess a relatively high impedance for the high level signal that is to be transferred by the transistor. If the data line D₀ is at the high level, the transfer speed of the data signal transferred to the common data line CD through MOSFET Q₁₃ becomes relatively lower.

If the high level of the data line D₀ is reduced to a relatively low level by MOSFET Q₁₇ as described above, MOSFET Q₁₃ comes to possess a relatively low impedance when it is turned ON by the selection signal Y₀. As a result, the transfer speed of the data signal can be increased.

The level shift voltage caused by the N-channel MOSFET Q₁₇ substantially increases the impedance change ratio of the P-channel MOSFET Q₁₈ as the variable impedance element. Thus, the power source voltage V_(cc) is supplied to the source of MOSFET Q₁₈ after its level is shifted by MOSFET Q₁₇. Therefore, when the power source voltage V_(cc) changes, the relative change ratio of the voltage applied across the source and gate of MOSFET Q₁₈ becomes greater than the change ratio of the power source voltage V_(cc) of its own. As a result, the impedance change ratio of MOSFET Q₁₈ becomes greater.

In this embodiment, since the P-channel MOSFET Q₁₈ (Q₂₀) whose conductance becomes smaller with the drop of the power source voltage V_(cc) is provided, compensation of the combined conductance characteristics of the load circuit becomes possible. Therefore, the read-out level (ΔV) of the memory cell MC can be kept substantially constant as represented by a solid line in FIG. 3. Since MOSFETs Q₁₇ and Q₁₈, Q₂₀) are provided, the conductance of MOSFET Q₉ (Q₁₀) described above is set to be smaller than that of MOSFET Q₉ shown in FIG. 1.

If the memory cell in this embodiment is the same as that in the first embodiment, the W/L ratios of MOSFETs Q₅, Q₉ and Q₁₈ assume the values of about 2.3/10, 3.3/2 and 25/2, respectively. The P-channel MOSFET Q₁₈ has a threshold voltage of -0.8 V, for example. The W/L ratio of MOSFET Q₁₇ as the level shift element is set to be about 67/2, for example, so that its impedance is sufficiently smaller than the impedance of MOSFET Q₁₈, though this is not particularly limited to this configuration.

In accordance with this second embodiment, the current path formed by MOSFETs Q₁₇, Q₁₈ and the current path formed by MOSFET Q₁₉ are simultaneously turned ON and OFF by the control signals WE·CS and WE·CS, respectively. Both MOSFETs Q₁₇ and Q₁₉ are of the N-channel type and their gates are connected to their drains. In other words, both MOSFETs Q₁₇ and Q₁₉ are diode-connected. Therefore, MOSFET Q₉ can be eliminated by increasing the impedance of MOSFET Q₁₇. Likewise, MOSFET Q₁₀ can be eliminated. However, if the MOSFETs Q₉ and Q₁₀ are eliminated, the following must be taken into consideration in this case.

Since the source potential of MOSFET Q₁₈ is reduced by MOSFET Q₁₇, its impedance is increased drastically at a relatively early stage of the start of drop of the power source voltage V_(cc). In other words, the current supplied to the data line D₀ through MOSFET Q₁₈ decreases drastically with the drop of the power source voltage V_(cc). The current path of MOSFETs Q₁₇ and Q₁₈ is substantially cut OFF when the power source voltage V_(cc) is substantially equal to the sum of the threshold voltages of these two transistors. Therefore, when the power source voltage V_(cc) drops, the low level of the data line D₀ determined by the memory cell drastically drops. This means that the voltage difference between the data lines D₀ and D₀ rather with the drop of the power source voltage V_(cc).

However, the increase of the level difference between the data lines D₀ and D₀ means the increase of time of change of each data line from the high level to the low and vice versa, and means also the increase of the access time of the memory during continuous read-out operation of a plurality of data.

Therefore, when the increase of the access time of the memory cell is not desired, it is desirable to employ the MOSFETs Q₉ and as shown in FIG. 2. The MOSFETs Q₉ and Q₁₀ form a current path even when power source voltage V_(cc) drops relatively greatly. Therefore, the MOSFETs Q₉ and Q₁₀ prevent the undesirable increase of the level difference between the data lines D₀ and D₀ brought forth by the change of impedance of MOSFET Q₁₈.

The circuit shown in FIG. 2 can be modified. For example, it is possible to directly connect the source of MOSFET Q₁₈ to the power source terminal V_(cc) and to interpose the diode-connection MOSFET Q₁₇ between the drain of Q₁₈ and the data line D₀. If this change is employed, the impedance change ratio of MOSFET Q₁₈ becomes relatively small.

[Embodiment 3]

FIG. 4 is a circuit diagram showing still another example of the load circuit for the data lines of the memory array described above. In this embodiment, P-channel MOSFETs Q₂₃ and Q₂₄ connected in the latch form and P-channel MOSFETs Q₂₁ and C₂₂ interposed between the sources of the former and the power source voltage V_(cc) are disposed in place of the load MOSFETs Q₅ and Q₆ in FIG. 1, respectively. The internal control signal WE·CS is applied to the gates of MOSFETs Q₂₁, Q₂₂ so that they are turned ON only in the write-in operation. The N-channel MOSFETs Q₂₅ and Q₂₆ are analogous to the N-channel MOSFETs Q₉ and Q₁₀ in FIG. 1 or 2. However, their conductance is set to be relatively great because MOSFETs of the parallel connection are not provided.

In this embodiment, MOSFETs Q₂₅ and Q₂₆ are turned ON during the chip nonselection state and in the read-out operation, and the current necessary for the read-out operation is supplied to the complementary data lines D and D. In the write-in operation, on the other hand, MOSFETs Q₂₁ and Q₂₂ are turned ON instead of these MOSFETs Q₂₅ and Q₂₆. In this case, the read-out level supplied from the selected memory cell to the unselected complementary data lines is amplified by the positive feedback operation of MOSFETs Q₂₃ and Q₂₄ connected as the latches. Therefore, the load MOSFET Q₂₃ or Q₂₄ connected to the data line on the side of the data storage MOSFET of the memory cell which is turned ON is turned OFF (enters a high impedance state), so that the occurrence of d.c. current in the unselected complementary data lines in the write-in operation can be prevented. Incidentally, since a large write-in level is supplied from the write-in circuit WA to the selected complementary data lines, latch MOSFETs Q₂₃ and Q₂₄ operate in accordance with its write-in level.

In this embodiment, if the conductance of Q₂₁ -Q₂₄ is less than the conductance of Q₂₅ and Q₂₆, a steady ground level may be applied to the gates of Q₂₁ and Q₂₂ instead of applying the WE·CS signal. In this case, all the MOSFETs Q₂₁, Q₂₂, Q₂₅ and Q₂₆ are turned ON in the read-out operation, but the level of the data lines is determined by Q₂₅ and Q₂₆ because of the difference of conductance.

The present invention can provide the following effects.

(1) The variable impedance means is used as the load circuit of the complementary data lines in the memory cell array, and its impedance is reduced in the read-out operation and when the chip is not being accessed. Therefore, the level difference of the complementary data lines due to the data stored in memory is reduced to the minimum necessary level. Since reset of the complementary data lines in the previous operation cycle is effected at a high sped, the memory operation can be speed up.

(2) Since a variable impedance means is used as the load circuit for the complementary data lines in the memory cell array, impedance is increased only in the write-in operation so that any wasteful current which would otherwise flow from the unselected complementary data lines through the selected memory cell can be reduced, and hence lower power consumption can be accomplished.

(3) In the read-out operation of the memory cells, the word lines are brought into the non-selection state after the read-out of the data stored in the memory cell to the complementary data lines and in the chip non-selection period, and the occurrence of the wasteful current flowing otherwise from the complementary data lines through the memory cell can be prevented. Therefore, lower power consumption can be accomplished.

(4) Due to the synergistic effect of (2) and (3), extremely low power consumption can be accomplished.

Although the invention has thus been described with reference to some preferred embodiments thereof, the invention is not particularly limited thereto but can, of course, be changed or modified in various ways. For example, the memory cell may use a static type flip-flop circuit comprising a combination of P-channel MOSFETs with N-channel MOSFETs. The load MOSFETs Q₅ to Q₈ may be replaced by resistance means such as polysilicon. The definite construction of the memory cell array and the definite circuit construction of its peripheral circuit can be embodied in various forms.

MOSFETs Q₂₅ and Q₂₆ shown in FIG. 4 may be replaced by MOSFETs Q₁₇ through Q₂₀ such shown in FIG. 2.

In the memory cell shown in FIGS. 1 and 2, the flip-flop circuit comprising the high resistance elements R₁, R₂ and MOSFETs Q₁, Q₂ can be replaced by a CMOS type flip-flop circuit consisting of two CMOS inverter circuits whose inputs and outputs are cross-connected. In other words, the memory cell using the high resistance elements (hereinafter called the "high resistance memory cell") such as those used in the foregoing embodiments can be changed to the CMOS type memory cell. The CMOS type memory cell needs low power consumption in the same way as the high resistance memory cell. In the CMOS memory cell, the MOSFETs that correspond to the high resistance elements constitute active load elements. Therefore, the CMOS type memory cell has a relatively large driving capacity for the data lines that are to be raised to the high level, unlike the high resistance memory. The drop of the level of the unselected data lines in the data write-in operation can therefore be prevented substantially by the CMOS type memory cell. Therefore, when the CMOS type memory cell is used, MOSFETs Q₅ through Q₈ shown in FIGS. 1 and 2 may be deleted.

The present invention can be applied widely to MOS static type RAMs. 

What is claimed is:
 1. An MOS static RAM comprising:a plurality of static memory cells; a pair of complementary data lines to which data input-output terminals of the static memory cells are connected; a plurality of word lines to which the selection terminals of said static memory cells are connected, respectively; variable load means coupled between a power supply terminal of the static RAM and the complementary data lines, respectively, the variable load means being constructed to be controlled such that their impedance becomes higher in a data write-in operation than the impedance thereof in a data read-out operation; selection means for selecting one of said plurality of word lines; and control means for controlling the state of the selected word line in the read-out operation so that the selected state of the word line is held during a period from the start of the selection of the word line to the time when there is a predetermined difference in the level difference between the pair of complementary data lines to be changed in accordance with the data stored in a static memory cell to which the selected word line is coupled, the selected word line being brought into an unselected state after the period.
 2. An MOS static RAM according to claim 1, further comprising a control circuit for controlling said variable load means, each of said variable load means comprising a resistance element forming a current path between a corresponding complementary data line and the power supply terminal, and a first MISFET whose gate electrode is connected so as receive the output signal of the control circuit, the first MISFET being arranged to be turned on in a read-out operation thereby to form a current path between the complementary data line and the power supply terminal, said first MISFET being arranged to be turned off in the write-in operation.
 3. An MOS static RAM according to claim 2, wherein each of the load and resistance elements is a polysilicon resistance element.
 4. An MOS static RAM according to claim 2, wherein each of the static memory cells comprises a pair of MOSFETs whose gate and drain electrodes are mutually cross-connected, load elements connected to the drain electrodes of the pair of MOSFETs, and a transfer gate MOSFET between the drain electrodes of the pair of MOSFETs and the complementary data line.
 5. An MOS static RAM according to claim 4, wherein each of the resistance elements has a diode-connected first MOSFET in the enhancement mode.
 6. An MOS static RAM according to claim 5, which further comprises a pair of common complementary data lines and third and fourth MOSFETs coupled between the complementary data lines and the pair of common complementary data lines, respectively, the third and fourth MOSFETs being arranged to receive selection signals at the gate electrodes thereof, each of the third and fourth MOSFETs having a channel conductivity type which is turned on by a selection signal of a level substantially equal to the power source voltage of the static RAM.
 7. An MOS static RAM according to claim 6, wherein the pair of MOSFETs of each memory cell and the third and fourth MOSFETs have the same channel conductivity type.
 8. An MOS static RAM according to claim 2, 4 or 5, wherein each of the variable load means further comprises a level shift element connected in series with the first MISFET, and wherein the first MISFET has a channel conductivity type which is turned on by a gate potential of a level substantially equal to a ground potential of the static RAM.
 9. An MOS static RAM according to claim 8, wherein each variable load means further comprises a second MISFET which forms a current path between the power terminal and the complementary data line in the read-out operation, the second MISFET being arranged to be turned off in the write-in operation, the second MISFET having a channel conductivity type opposite to that of the first MISFET.
 10. An MOS static RAM according to claim 9, wherein the level shift element has a diode-connected third MOSFET having a channel conductivity type opposite to that of the first MISFET.
 11. An MOS static RAM according to claim 10, further comprising a pair of common complementary data lines, and fourth and fifth MOSFETs coupled between the complementary data lines and the common complementary data lines, respectively, the fourth and fifth MOSFETs being arranged to receive selection signals at the gate electrodes thereof, each of the fourth and fifth MOSFETs having the same channel conductivity type as that of the second and third MOSFETs.
 12. An MOS static RAM according to claim 8, wherein the level shift element is coupled between the source electrode of the first MISFET and the power supply terminal.
 13. An MOS static RAM according to claim 8, wherein the level shift element is a diode-connected second MOSFET.
 14. An MOS static RAM according to claim 13, wherein the second MOSFET and the pair of MOSFETs of each memory cells have a channel conductivity type opposite to that of the first MISFET.
 15. An MOS static RAM according to claim 1, wherein the variable load means has first and second MOSFETs coupled between the power supply terminal and said complementary data lines, respectively, the gate and drain electrodes thereof being mutually cross-connected, and third and fourth MOSFETs coupled between the power supply terminal and said complementary data lines, respectively, each of the third and fourth MOSFETs being turned off in the data write-in operation and being turned on in the data read-out operation.
 16. An MOS static RAM according to claim 15, which further comprises fifth and sixth MOSFETs connected in series with said first and second MOSFETs, each of said fifth and sixth MOSFETs being controlled so that it is turned on and off at substantially the same time as the third and fourth MOSFETs.
 17. An MOS static RAM according to claim 1, wherein the selection means includes an address decoder adapted to generate selection signals to be supplied to the word lines; and comprising a further control means arranged to receive at least a chip selection signal, and arranged to set the output of the address decoder to a non-selection level in a chip non-selection state.
 18. An MOS static RAM comprising:a plurality of static memory cells; a pair of complementary data lines to which data input-output terminals of the static cells are connected; a plurality of word lines to which the selection terminals of said static type memory cells are connected, respectively; variable load means coupled between a power supply terminal of the static RAM and the complementary data lines, respectively, wherein said variable load means includes means responsive to a control signal for reducing the impedance of the variable load means during a data read-out operation; selection means for selecting one of said plurality of word lines; and control means for controlling the state of the selected word line in the read-out operation so that the selected state of the word line is held during a period from the start of the selection of the word line to the time when there is a predetermined difference in the level difference between the pair of complementary data lines to be changed in accordance with the data stored in a static memory cells to which the selected word line is coupled, the selected word line being brought into an unselected state after the period.
 19. An MOS static RAM according to claim 18, further comprising a control circuit for controlling the load means, each of the load means comprising a resistance element forming a current path between a corresponding complementary data line and the power supply terminal, and a first MISFET whose gate electrode is connected so as to receive the output signal of the control circuit, the first MISFET being arranged to be turned on in a read-out operation thereby to form a current path between the complementary data line and the power supply terminal, said first MISFET being arranged to be turned off in the write-in operation.
 20. An MOS static RAM according to claim 19, wherein each of the static memory cells comprises a pair of MOSFETs whose gate and drain electrodes are mutually cross-connected, load elements connected to the drain electrodes of the pair of MOSFETs, and a transfer gate MOSFET between the drain electrodes of the pair of MOSFETs and the complementary data line.
 21. An MOS static RAM according to claim 20, wherein each of the load and resistance elements is a polysilicon resistance element.
 22. An MOS static RAM according to claim 20, wherein each of the resistance elements has a diode-connected first MOSFET in the enhancement mode.
 23. An MOS static RAM according to claim 22, which further comprises a pair of common complementary data lines and third and fourth MOSFETs coupled between the complementary data lines and the pair of common complementary data lines, respectively, the third and fourth MOSFETs being arranged to receive selection signals at the gate electrodes thereof, each of the third and fourth MOSFETs having a channel conductivity type which is turned on by a selection signal of a level substantially equal to the power source voltage of the static RAM.
 24. An MOS static RAM according to claim 23, wherein the pair of MOSFETs of each memory cell and the third and fourth MOSFETs have the same channel conductivity type.
 25. An MOS static RAM according to claim 19, wherein each of the load means further comprises a level shift element connected in series with the first MISFET, and wherein the first MISFET has a channel conductivity type which is turned on by a gate potential of a level substantially equal to a ground potential of the static RAM.
 26. An MOS static RAM according to claim 25, wherein the level shift element is coupled between the source electrode of the first MISFET and the power supply terminal.
 27. An MOS static RAM according to claim 26, wherein the level shift element is a diode-connected second MOSFET.
 28. An MOS static RAM according to claim 27, wherein the second MOSFET and the pair MOSFETs of each memory cell have a channel conductivity type opposite to that of the first MISFET.
 29. An MOS static RAM according to claim 25, wherein each load means further comprises a second MISFET which forms a current path between the power terminal and the complementary data line in the read-out operation, the second MISFET being arranged to be turned off in the write-in operation, the second MISFET having a channel conductivity type opposite to that of the first MISFET.
 30. An MOS static RAM according to claim 29, wherein the level shift element has a diode-connected third MOSFET having a channel conductivity type opposite to that of the first MISFET.
 31. An MOS static RAM according to claim 30, further comprising a pair of common complementary data lines, and fourth and fifth MOSFETs coupled between the complementary data lines and the common complementary data lines, respectively, the fourth and fifth MOSFETs being arranged to receive selection signals at the gate electrodes thereof, each of the fourth and fifth MOSFETs having the same channel conductivity type as that of the second and third MOSFETs.
 32. An MOS static RAM according to claim 18, wherein the load means has first and second MOSFETs coupled between the power supply terminal and said complementary data lines, respectively, the gate and drain electrodes thereof being mutually cross-connected, and third and fourth MOSFETs coupled between the power supply terminal and said complementary data lines, respectively, each of the third and fourth MOSFETs being turned off in the data write-in operation and being turned on in the data read-out operation.
 33. An MOS static RAM according to claim 32, which further comprises fifth and sixth MOSFETs connected in series with said first and second MOSFETs, each of said fifth and sixth MOSFETs being controlled so that it is turned on and off at substantially the same time as the third and fourth MOSFETs.
 34. An MOS static RAM according to claim 18, wherein the selection means includes an address decoder adapted to generate selection signals to be supplied to the word lines; and comprising a further control means arranged to receive at least a chip selection signal, and arranged to set the output of the address decoder to a non-selection level in a chip non-selection state. 